34 lines
1.5 KiB
Diff
34 lines
1.5 KiB
Diff
From: Matthias Schiffer <mschiffer@universe-factory.net>
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Date: Fri, 13 May 2016 22:58:50 +0200
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Subject: ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
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Incorrect value causes clock inaccuracy as huge as 1/60.
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Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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Backport of OpenWrt r47363
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diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
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index b5c88e9..d3a14b2 100644
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--- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
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+++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
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@@ -529,7 +529,7 @@
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+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
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+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
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+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
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-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
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++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
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+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
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+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
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+
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@@ -541,7 +541,7 @@
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+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
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+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
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+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
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-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
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++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
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+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
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+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
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+
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